R5F21266SNFP#U0 Renesas Electronics America, R5F21266SNFP#U0 Datasheet - Page 323

• Manufacturer Part Number: R5F21266SNFP#U0
• Description: IC R8C/26 MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/26r

Specifications of R5F21266SNFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 32KB (32K x 8)
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• No. Of I/o's: 25
• Ram Memory Size: 1.5KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 2.2V To 5.5V
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 16.32
Figure 16.33
(slave output)
ICSR register
ICSR register
(master output)
(master output)
ICDRS register
ICDRT register
(master output)
(master output)
(slave output)
ICSR register
ICSR register
TDRE bit in
TEND bit in
ICDRS register
ICDRT register
Sep 26, 2008
TDRE bit in
TEND bit in
by program
Processing
by program
Processing
SDA
SDA
SDA
SCL
SDA
SCL
Operating Timing in Master Transmit Mode (I
Operating Timing in Master Transmit Mode (I
1
0
1
0
1
0
1
0
(2) Instruction of
(3) Data write to ICDRT
start condition
generation
register
Page 304 of 453
9
A
b7
1
b7
1
b6
(3) Data write to ICDRT
2
register (1st byte)
b6
2
b5
3
b5
Slave address
3
Address + R/W
b4
4
b4
4
Address + R/W
Data n
b3
5
Data n
b3
5
b2
(4) Data write to ICDRT
6
register (2nd byte)
b2
6
b1
7
2
2
C bus Interface Mode) (1)
C bus Interface Mode) (2)
b1
7
b0
R/W
8
(6) Generate stop condition and
16. Clock Synchronous Serial Interface
b0
set TEND bit to 0
8
A
9
A/A
9
(7) Set to slave receive mode
(5) Data write to ICDRT
register (3rd byte)
Data 1
Data 1
b7
1
Data 2
b6
2