MC908AP64CFAER Freescale Semiconductor, MC908AP64CFAER Datasheet - Page 83
![IC MCU 64K FLASH 8MHZ 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC908AP64CFAER
Manufacturer Part Number
MC908AP64CFAER
Description
IC MCU 64K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP8CFBE.pdf
(324 pages)
Specifications of MC908AP64CFAER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
HC08AP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908AP64E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908AP64CFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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6.3.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
Automatic mode is recommended for most users.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See
Bandwidth Control
request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit
continuously (during PLL start-up, usually) or at periodic intervals. In either case, when the LOCK bit is
set, the VCO clock is safe to use as the source for the base clock. (See
If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the application. (See
Interrupts
The following conditions apply when the PLL is in automatic bandwidth control mode:
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
f
The following conditions apply when in manual mode:
6.3.6 Programming the PLL
The following procedure shows how to program the PLL.
Freescale Semiconductor
BUSMAX
•
•
•
•
•
•
•
•
•
•
The ACQ bit (See
the filter. (See
The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See
more information.)
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See
more information.)
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. (See
ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ bit must be clear.
Before entering tracking mode (ACQ = 1), software must wait a given time, t
Acquisition/Lock Time
control register (PCTL).
Software must wait a given time, t
clock source to CGMOUT (BCS = 1).
The LOCK bit is disabled.
CPU interrupts from the CGM are disabled.
.
for information and precautions on using interrupts.)
The round function in the following equations means that the real number
should be rounded to the nearest integer number.
Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
6.3.4 Acquisition and Tracking
6.5.2 PLL Bandwidth Control
6.5.1 PLL Control
Specifications.), after turning on the PLL by setting PLLON in the PLL
MC68HC908AP Family Data Sheet, Rev. 4
AL
, after entering tracking mode before selecting the PLL as the
Register.)
NOTE
Modes.)
Register.) is a read-only indicator of the mode of
6.8 Acquisition/Lock Time Specifications
6.8 Acquisition/Lock Time Specifications
6.3.8 Base Clock Selector
ACQ
Functional Description
(See
6.5.2 PLL
6.8
Circuit.)
for
for
6.6
83
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