C8051F500-IM Silicon Laboratories Inc, C8051F500-IM Datasheet - Page 221
![IC 8051 MCU 64K FLASH 48-QFN](/photos/12/36/123639/c8051f500-im_sml.jpg)
C8051F500-IM
Manufacturer Part Number
C8051F500-IM
Description
IC 8051 MCU 64K FLASH 48-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F500-IM
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
48-QFN
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1530 - ADAPTER PROG TOOLSTICK F500336-1529 - PLATFORM PROG TOOLSTCK F500336-1527 - KIT DEV FOR C8051F50X336-1526 - BOARD PROTOTYPE W/C8051F500
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1511-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F500-IM
Manufacturer:
Silicon Labs
Quantity:
135
Part Number:
C8051F500-IMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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The length of the 4 bit segments must be adjusted so that their sum is as close as possible to the desired
bit time. Since each segment must be an integer multiple of the time quantum (t
bit time is 24 tq (1000.008 ns), yielding a bit rate of 0.999992 Mbit/sec. The Sync_Seg is a constant 1 tq.
The Prop_Seg must be greater than or equal to the propagation delay of 400 ns and so the choice is 10 tq
(416.67 ns).
The remaining time quanta (13 tq) in the bit time are divided between Phase_Seg1 and Phase_Seg2 as
shown in. Based on this equation, Phase_Seg1 = 6 tq and Phase_Seg2 = 7 tq.
The Synchronization Jump Width (SJW) timing parameter is defined by. It is used for determining the value
written to the Bit Timing Register and for determining the required oscillator tolerance. Since we are using
a quartz crystal as the system clock source, an oscillator tolerance calculation is not needed.
The value written to the Bit Timing Register can be calculated using Equation 18.3. The BRP Extension
register is left at its reset value of 0x0000.
Bit Timing Register = (TSEG2 x 0x1000) + (TSEG1 x 0x0100) + (SJWp x 0x0040) + BRPE = 0x6FC0
1. If Phase_Seg1 + Phase_Seg2 is even, then Phase_Seg2 = Phase_Seg1. If the sum is odd,
2. Phase_Seg2 should be at least 2
Phase_Seg2 = Phase_Seg1 + 1.
1t
Phase_Seg1 + Phase_Seg2 = Bit_Time – (Synch_Seg + Prop_Seg)
Equation 22.3. Calculating the Bit Timing Register Value
q
Bit Timing Register = (TSEG2 x 0x1000) + (TSEG1 x 0x0100)
Equation 22.2. Synchronization Jump Width (SJW)
Sync_Seg
TSEG1 = Prop_Seg + Phase_Seg1 - 1 = 10 + 6 – 1 = 15
Equation 22.1. Assigning the Phase Segments
BRPE = BRP – 1 = BRP Extension Register = 0x0000
1t
Prop_Seg
Figure 22.3. Four segments of a CAN Bit
1 to 8 t
q
SJWp = SJW – 1 = minimum (4, 6) – 1 = 3
SJW = minimum (4, Phase_Seg1)
t
TSEG2 = Phase_Seg2 – 1 = 6
q
q
CAN Bit Time (4 to 25 t
.
Rev. 1.1
Phase_Seg1
1 to 8 t
q
q
)
C8051F50x-F51x
Phase_Seg2
Sample Point
1 to 8 t
q
), the closest achievable
q
221
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