C8051F500-IM Silicon Laboratories Inc, C8051F500-IM Datasheet - Page 101
![IC 8051 MCU 64K FLASH 48-QFN](/photos/12/36/123639/c8051f500-im_sml.jpg)
C8051F500-IM
Manufacturer Part Number
C8051F500-IM
Description
IC 8051 MCU 64K FLASH 48-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F500-IM
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
48-QFN
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1530 - ADAPTER PROG TOOLSTICK F500336-1529 - PLATFORM PROG TOOLSTCK F500336-1527 - KIT DEV FOR C8051F50X336-1526 - BOARD PROTOTYPE W/C8051F500
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1511-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F500-IM
Manufacturer:
Silicon Labs
Quantity:
135
Part Number:
C8051F500-IMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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C8051F50x-F51x
SFRPGCN Bit
Interrupt
Logic
SFRPAGE
CIP-51
SFRNEXT
SFRLAST
Figure 13.1. SFR Page Stack
Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using
the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFR0CN). This
function defaults to “enabled” upon reset. In this way, the autoswitching function will be enabled unless dis-
abled in software.
A summary of the SFR locations (address and SFR page) are provided in Table 13.3 in the form of an SFR
memory map. Each memory location in the map has an SFR page row, denoting the page in which that
SFR resides. Certain SFRs are accessible from ALL SFR pages, and are denoted by the “(ALL PAGES)”
designation. For example, the Port I/O registers P0, P1, P2, and P3 all have the “(ALL PAGES)” designa-
tion, indicating these SFRs are accessible from all SFR pages regardless of the SFRPAGE register value.
13.3. SFR Page Stack Example
The following is an example that shows the operation of the SFR Page Stack during interrupts. In this
example, the SFR Control register is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51
is executing in-line code that is writing values to SPI Data Register (SFR “SPI0DAT”, located at address
0xA3 on SFR Page 0x00). The device is also using the CAN peripheral (CAN0) and the Programmable
Counter Array (PCA0) peripheral to generate a PWM output. The PCA is timing a critical control function in
its interrupt service round so its associated ISR that is set to low priority. At this point, the SFR page is set
to access the SPI0DAT SFR (SFRPAGE = 0x00). See Figure 13.2.
Rev. 1.1
101
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