R5F21292SNSP#U0 Renesas Electronics America, R5F21292SNSP#U0 Datasheet - Page 148

• Manufacturer Part Number: R5F21292SNSP#U0
• Description: MCU 3/5V 16K+2K 20PIN-SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/29r

Specifications of R5F21292SNSP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/28 Group, R8C/29 Group
Rev.2.10
REJ09B0279-0210
13. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows
selection of count source protection mode enable or disable.
Table 13.1 lists information on the Count Source Protection Mode.
Refer to 5.7 Watchdog Timer Reset for details on the watchdog timer.
Figure 13.1 shows the Block Diagram of Watchdog Timer. Figure 13.2 shows Registers OFS and WDC. Figure 13.3
shows Registers WDTR, WDTS, and CSPR.
Figure 13.1
Table 13.1
Count source
Count operation
Count start condition
Count stop condition
Reset condition of watchdog
timer
Operation at the time of underflow Watchdog timer interrupt or
CPU clock
NOTE:
Sep 26, 2008
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
Write to WDTR register
reset signal
Count Source Protection Mode
Block Diagram of Watchdog Timer
Item
Internal
Page 129 of 441
Prescaler
1/128
1/16
CPU clock
Decrement
Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Stop mode, wait mode
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
watchdog timer reset
WDC7 = 0
Count Source Protection
WDC7 = 1
fOCO-S
Mode Disabled
CSPRO = 0
CSPRO = 1
Watchdog timer
Low-speed on-chip oscillator
clock
None
Watchdog timer reset
Count Source Protection
Set to
7FFFh
Mode Enabled
(1)
CSPRO: Bit in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
13. Watchdog Timer
PM12 = 0
Watchdog timer
interrupt request
PM12 = 1
Watchdog
timer reset