C8051F504-IQ Silicon Laboratories Inc, C8051F504-IQ Datasheet - Page 205

• Manufacturer Part Number: C8051F504-IQ
• Description: IC 8051 MCU 32K FLASH 48-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F504-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1518

21.3. LIN Master Mode Operation
The master node is responsible for the scheduling of messages and sends the header of each frame con-
taining the SYNCH BREAK FIELD, SYNCH FIELD, and IDENTIFIER FIELD. The steps to schedule a mes-
sage transmission or reception are listed below.
1. Load the 6-bit Identifier into the LIN0ID register.
2. Load the data length into the LIN0SIZE register. Set the value to the number of data bytes or "1111b" if
3. Set the data direction by setting the TXRX bit (LIN0CTRL.5). Set the bit to 1 to perform a master
4. If performing a master transmit operation, load the data bytes to transmit into the data buffer (LIN0DT1
5. Set the STREQ bit (LIN0CTRL.0) to start the message transfer. The LIN controller will schedule the
This code segment shows the procedure to schedule a message in a transmission operation:
The application should perform the following steps when an interrupt is requested.
the data length should be decoded from the identifier. Also, set the checksum type, classic or
enhanced, in the same LIN0SIZE register.
transmit operation, or set the bit to 0 to perform a master receive operation.
to LIN0DT8).
message frame and request an interrupt if the message transfer is successfully completed or if an error
has occurred.
LIN0ADR
LIN0DAT
LIN0ADR
LIN0DAT
LIN0ADR
LIN0DAT
LIN0ADR
for (i=0; i<8; i++)
{
}
LIN0ADR
LIN0DAT
LIN0DAT = i + 0x41;
LIN0ADR++;
|= 0x20;
= ( LIN0DAT & 0xF0 ) | 0x08;
= 0x00;
= 0x08;
= 0x01;
= 0x08;
= 0x0E;
= 0x11;
= 0x0B;
Table 21.3. Autobaud Parameters Examples
System Clock (MHz)
22.1184
11.0592
12.25
24.5
25
24
16
12
8
// Point to Data buffer first byte
// Load the buffer with ‘A’, ‘B’, ...
// Increment the address to the next buffer
// Point to LIN0CTRL
// Start Request
// Point to LIN0CTRL
// Select to transmit data
// Point to LIN0ID
// Load the ID, in this example 0x11
// Point to LIN0SIZE
Rev. 1.2
Prescaler
// Load the size with 8
1
1
1
1
1
0
0
0
0
Divider
C8051F50x/F51x
312
306
300
276
200
306
300
276
200
205