MC9S08DZ128MLF Freescale Semiconductor, MC9S08DZ128MLF Datasheet - Page 275
![MCU 8BIT 128K FLASH 48-LQFP](/photos/37/62/376254/lqfp-48_sml.jpg)
MC9S08DZ128MLF
Manufacturer Part Number
MC9S08DZ128MLF
Description
MCU 8BIT 128K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.MC9S08DV96CLF.pdf
(458 pages)
2.MC9S08DV96CLF.pdf
(4 pages)
3.MC9S08DZ128CLF.pdf
(4 pages)
Specifications of MC9S08DZ128MLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
87
Number Of Timers
3
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
24-ch x 12-bit
Controller Family/series
HCS08
No. Of I/o's
40
Eeprom Memory Size
2KB
Ram Memory Size
8KB
Cpu Speed
40MHz
No. Of Timers
3
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
A/d Bit Size
12 bit
A/d Channels Available
16
Height
1.4 mm
Length
7 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ128MLF
Manufacturer:
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Quantity:
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Part Number:
MC9S08DZ128MLF
Manufacturer:
Freescale Semiconductor
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Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
12.4
The following section details the organization of the receive and transmit message buffers and the
associated control registers.
To simplify the programmer interface, the receive and transmit message buffers have the same outline.
Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.
An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last
two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an
internal timer after successful transmission or reception of a message. This feature is only available for
transmit and receiver buffers if the TIME bit is set (see
(CANCTL0)”).
The time stamp register is written by the MSCAN. The CPU can only read these registers.
Freescale Semiconductor
AM[7:0]
AM[7:0]
Field
Field
7:0
7:0
Reset
W
Figure 12-22. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7
R
Programmer’s Model of Message Storage
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit (don’t care)
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit (don’t care)
AM7
0
7
Table 12-22. CANIDMR0–CANIDMR3 Register Field Descriptions
Table 12-23. CANIDMR4–CANIDMR7 Register Field Descriptions
AM6
0
6
MC9S08DZ128 Series Data Sheet, Rev. 1
AM5
0
5
AM4
0
4
Description
Description
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
Section 12.3.1, “MSCAN Control Register 0
AM3
0
3
AM2
0
2
AM1
1
0
AM0
0
0
275
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