MC908GR16VFAE Freescale Semiconductor, MC908GR16VFAE Datasheet - Page 74
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MC908GR16VFAE
Manufacturer Part Number
MC908GR16VFAE
Description
IC MCU 16K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Specifications of MC908GR16VFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR16VFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Clock Generator Module (CGM)
4.5.5 PLL VCO Range Select Register
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
VRS7–VRS0 — VCO Range Select Bits
4.5.6 PLL Reference Divider Select Register
The PLL reference divider select register (PMDS) contains the programming information for the modulo
reference divider.
74
These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with
E (see
hardware center-of-range frequency, f
PCTL is set. (See
register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See
Clock Selector Circuit
for a default range multiply value of 64.
4.3.3 PLL
Address:
Address:
The VCO range select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
Reset:
Reset:
Read:
Read:
Write:
Write:
Circuits,
Figure 4-9. PLL Reference Divider Select Register (PMDS)
4.3.7 Special Programming
$003A
$003B
VRS7
Bit 7
Bit 7
PMDS may be called PRDS on other HC08 derivatives.
PMRS may be called PVRS on other HC08 derivatives.
Figure 4-8. PLL VCO Range Select Register (PMRS)
0
and
0
0
4.3.7 Special Programming
4.3.6 Programming the
= Unimplemented
VRS6
6
1
6
0
0
MC68HC908GR16 Data Sheet, Rev. 4.0
VRS
VRS5
5
0
5
0
0
. VRS7–VRS0 cannot be written when the PLLON bit in the
NOTE
NOTE
NOTE
Exceptions.) A value of $00 in the VCO range select
VRS4
4
0
4
0
0
PLL, and
Exceptions.) Reset initializes the register to $40
VRS3
RDS3
3
0
3
0
4.5.1 PLL Control
VRS2
RDS2
2
0
2
0
VRS1
RDS1
1
0
1
0
Register), controls the
Freescale Semiconductor
VRS0
RDS0
Bit 0
Bit 0
0
1
4.3.8 Base
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