MC908GR16VFAE Freescale Semiconductor, MC908GR16VFAE Datasheet - Page 57
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MC908GR16VFAE
Manufacturer Part Number
MC908GR16VFAE
Description
IC MCU 16K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Specifications of MC908GR16VFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR16VFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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3.8.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADICLK — ADC Input Clock Select Bit
The ADC requires a clock rate of approximately 1 MHz for correct operation. If the selected clock source
is not fast enough, the ADC will generate incorrect conversions. See
and
MODE1 and MODE0 — Modes of Result Justification Bits
Freescale Semiconductor
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal
ADC clock.
approximately 1 MHz.
ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK) as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source.
MODE1 and MODE0 select among four modes of operation. The manner in which the ADC conversion
results will be placed in the ADC data registers is controlled by these modes of operation. Reset
returns right-justified mode.
20.11 3.3-Volt ADC
1 = Internal bus clock
0 = Oscillator output clock (CGMXCLK)
00 = 8-bit truncation mode
01 = Right justified mode
10 = Left justified mode
11 = Left justified signed data mode
Address:
Table 3-2
Reset:
Read:
Write:
$003F
ADIV2
Bit 7
1. X = Don’t care
Characteristics.
0
shows the available clock configurations. The ADC clock should be set to
ADIV2
0
0
0
0
1
f
ADIC
Figure 3-9. ADC Clock Register (ADCLK)
= Unimplemented
ADIV1
=
6
0
Table 3-2. ADC Clock Divide Ratio
MC68HC908GR16 Data Sheet, Rev. 4.0
ADIV1
f
X
CGMXCLK
0
0
1
1
(1)
ADIV0
5
0
ADIV[2:0]
ADIV0
or bus frequency
X
0
1
0
1
(1)
ADICLK
R
4
0
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
= Reserved
MODE1
3
0
ADC Clock Rate
MODE0
≅ 1 MHz
20.10 5.0-Volt ADC Characteristics
2
1
R
1
0
Bit 0
0
0
I/O Registers
57
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