MCF51JM64EVQH Freescale Semiconductor, MCF51JM64EVQH Datasheet - Page 28
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MCF51JM64EVQH
Manufacturer Part Number
MCF51JM64EVQH
Description
MCU 64K FLASH 16K SRAM 64-QFP
Manufacturer
Freescale Semiconductor
Series
MCF51JMr
Datasheet
1.MCF51JM64VLD.pdf
(50 pages)
Specifications of MCF51JM64EVQH
Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, I²C, SCI, SPI, USB OTG
Peripherals
LVD, PWM, WDT
Number Of I /o
51
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
64-QFP
Processor Series
MCF51JM
Core
ColdFire V1
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
DEMOJM, DEMOFLEXISJMSD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Preliminary Electrical Characteristics
2.11
This section describes ac timing characteristics for each peripheral system.
2.11.1
28
1
2
3
4
5
6
7
8
Num
Typical values are based on characterization data at V
This is the shortest pulse guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override
reset requests from internal sources.
This is the minimum pulse width guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not
be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% V
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V
a given interval.
625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN
bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge
and the sample point of a bit using 8 time quanta per bit.
Below D
MCG is already in lock, then the MCG may stay in lock.
Below D
1
2
3
4
5
6
7
8
9
C
lock
unl
AC Characteristics
Control Timing
minimum, the MCG will not exit lock if already in lock. Above D
Bus frequency (t
Internal low-power oscillator period
External reset pulse width
(t
Reset low drive
Active background debug mode latch setup time
Active background debug mode latch hold time
IRQ pulse width
KBIPx pulse width
Port rise and fall time (load = 50 pF)
Slew rate control disabled (PTxSE = 0) High drive
Slew rate control disabled (PTxSE = 0) Low drive
minimum, the MCG is guaranteed to enter lock. Above D
cyc
Asynchronous path
Synchronous path
Asynchronous path
Synchronous path
Slew rate control enabled (PTxSE = 1) High drive
Slew rate control enabled (PTxSE = 1) Low drive
= 1/f
Self_reset
cyc
)
= 1/f
3
3
Parameter
2
2
DD
MCF51JM128 ColdFire Microcontroller, Rev. 3
Bus
and V
2
DD
)
and 80% V
SS
Table 17. Control Timing
and variation in crystal oscillator frequency increase the C
4
DD
DD
levels. Temperature range –40°C to 105°C.
= 5.0V, 25°C unless otherwise stated.
t
t
t
Symbol
ILIH,
ILIH,
Rise
t
t
t
t
MSSU
lock
t
f
extrst
rstdrv
MSH
LPO
Bus
, t
t
t
IHIL
IHIL
maximum, the MCG will not enter lock. But if the
Fall
unl
maximum, the MCG is guaranteed to exit lock.
1.5 x t
1.5 × t
66 × t
Min
700
100
500
100
100
100
dc
—
cyc
cyc
cyc
Typ
11
35
40
75
—
—
—
—
—
—
—
—
1
Freescale Semiconductor
Jitter
1300
Max
24
—
—
—
—
—
—
—
percentage for
BUS
MHz
Unit
.
μs
ns
ns
ns
ns
ns
ns
ns