S9S12P96J0MFT Freescale Semiconductor, S9S12P96J0MFT Datasheet - Page 98
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S9S12P96J0MFT
Manufacturer Part Number
S9S12P96J0MFT
Description
MCU 96K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P96J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1. Read: Anytime
1. Read: Anytime
Port Integration Module (S12PPIMV1)
2.3.60
2.3.61
98
Address 0x0273
DDR1AD
Address 0x0274
RDR0AD
Write: Anytime
Write: Anytime
Field
Field
Reset
Reset
7-0
1-0
W
W
R
R
DDR1AD7
Port AD data direction—
This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATDDIEN) has to be set to logic level “1”.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port AD reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Port AD Data Direction Register (DDR1AD)
Port AD Reduced Drive Register (RDR0AD)
0
0
0
7
7
DDR1AD6
Figure 2-59. Port AD Reduced Drive Register (RDR0AD)
Figure 2-58. Port AD Data Direction Register (DDR1AD)
0
0
0
6
6
Table 2-54. DDR1AD Register Field Descriptions
Table 2-55. RDR0AD Register Field Descriptions
DDR1AD5
S12P-Family Reference Manual, Rev. 1.13
5
0
5
0
0
DDR1AD4
0
0
0
4
4
Description
Description
DDR1AD3
0
0
0
3
3
DDR1AD2
0
0
0
2
2
DDR1AD1
RDR0AD1
Access: User read/write
Access: User read/write
Freescale Semiconductor
0
0
1
1
DDR1AD0
RDR0AD0
0
0
0
0
(1)
(1)
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