S9S12P96J0MFT Freescale Semiconductor, S9S12P96J0MFT Datasheet - Page 160
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S9S12P96J0MFT
Manufacturer Part Number
S9S12P96J0MFT
Description
MCU 96K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P96J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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S12S Debug Module (S12SDBGV2)
6.3.2.2
160
Address: 0x0021
DBGBRK
COMRV
Reset
Field
TRIG
ARM
BDM
POR
1–0
7
6
4
3
W
R
Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user
software and is automatically cleared on completion of a debug session, or if a breakpoint is generated with
tracing not enabled. On setting this bit the state sequencer enters State1.
0 Debugger disarmed
1 Debugger armed
Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of state
sequencer status. When tracing is complete a forced breakpoint may be generated depending upon DBGBRK
and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If the
DBGTCR_TSOURCE bit is clear no tracing is carried out. If tracing has already commenced using BEGIN trigger
alignment, it continues until the end of the tracing session as defined by the TALIGN bit, thus TRIG has no affect.
In secure mode tracing is disabled and writing to this bit cannot initiate a tracing session.
The session is ended by setting TRIG and ARM simultaneously.
0 Do not trigger until the state sequencer enters the Final State.
1 Trigger immediately
Background Debug Mode Enable — This bit determines if a breakpoint causes the system to enter Background
Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the
ENBDM bit in the BDM module, then breakpoints default to SWI.
0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
S12SDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint
0 No Breakpoint generated
1 Breakpoint generated
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the
8-byte window of the S12SDBG module address map, located between 0x0028 to 0x002F. Furthermore these
bits determine which register is visible at the address 0x0027. See
TBF
Debug Status Register (DBGSR)
—
0
7
on reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion
of the tracing session. If tracing is not enabled, the breakpoint is generated immediately.
COMRV
00
01
10
11
= Unimplemented or Reserved
0
0
0
6
Figure 6-4. Debug Status Register (DBGSR)
Visible Comparator
S12P-Family Reference Manual, Rev. 1.13
Table 6-3. DBGC1 Field Descriptions
Comparator A
Comparator B
Comparator C
0
0
0
5
Table 6-4. COMRV Encoding
None
0
0
0
4
Description
Visible Register at 0x0027
0
0
0
3
Table
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
SSF2
6-4.
0
0
2
Freescale Semiconductor
SSF1
0
0
1
SSF0
0
0
0
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