MC9S08GT32ACFDER Freescale Semiconductor, MC9S08GT32ACFDER Datasheet - Page 79
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MC9S08GT32ACFDER
Manufacturer Part Number
MC9S08GT32ACFDER
Description
MCU 8BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08GT60ACFDER.pdf
(302 pages)
Specifications of MC9S08GT32ACFDER
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S08GT
Core
HCS08
3rd Party Development Tools
EWS08
Development Tools By Supplier
M68EVB908GB60E, M68DEMO908GB60E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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1
5.8.7
Freescale Semiconductor
This bit can be written only one time after reset. Additional writes are ignored.
LVDACK
Reset
LVDRE
LVDSE
LVDIE
LVDE
Field
LVDF
7
6
5
4
3
2
W
R
System Power Management Status and Control 1 Register (SPMSC1)
LVDF
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
0
7
= Unimplemented or Reserved
LVDACK
0
0
6
Table 5-10. SPMSC1 Field Descriptions
LVDIE
MC9S08GB60A Data Sheet, Rev. 2
0
5
LVDRE
1
4
1
Description
LVDSE
Chapter 5 Resets, Interrupts, and System Configuration
3
1
(1)
LVDE
1
2
(1)
0
0
1
0
0
0
79
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