C8051F330-GMR Silicon Laboratories Inc, C8051F330-GMR Datasheet - Page 86
C8051F330-GMR
Manufacturer Part Number
C8051F330-GMR
Description
IC 8051 MCU 8K FLASH 20MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F330-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
For Use With
336-1541 - KIT TOOL EVAL SYS IN A USB STICK336-1451 - ADAPTER PROGRAM TOOLSTICK F330336-1346 - DAUGHTER CARD TOOLSTICK F330336-1264 - DEV KIT FOR C8051F330/F331
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F330-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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9.3.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
EA
Bit7
EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set-
tings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
EX1: Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
EX0: Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 input.
ESPI0
R/W
Bit6
SFR Definition 9.7. IE: Interrupt Enable
ET2
R/W
Bit5
ES0
R/W
Bit4
Rev. 1.7
ET1
R/W
Bit3
EX1
R/W
Bit2
C8051F330/1/2/3/4/5
ET0
R/W
Bit1
(bit addressable)
EX0
R/W
Bit0
SFR Address:
00000000
Reset Value
0xA8
89
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