C8051F330-GMR Silicon Laboratories Inc, C8051F330-GMR Datasheet - Page 145
C8051F330-GMR
Manufacturer Part Number
C8051F330-GMR
Description
IC 8051 MCU 8K FLASH 20MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F330-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
For Use With
336-1541 - KIT TOOL EVAL SYS IN A USB STICK336-1451 - ADAPTER PROGRAM TOOLSTICK F330336-1346 - DAUGHTER CARD TOOLSTICK F330336-1264 - DEV KIT FOR C8051F330/F331
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F330-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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15.5.3. Slave Receiver Mode
Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH =
0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit
(WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the
ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received
slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until
the next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received. Software must write the ACK bit after each received byte to ACK or NACK the received byte. The
interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 15.7 shows a typical Slave
Receiver sequence. Two received data bytes are shown, though any number of bytes may be received.
Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode.
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 15.7. Typical Slave Receiver Sequence
SLA
Interrupt
W
A
Data Byte
Rev. 1.7
Interrupt
A
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
C8051F330/1/2/3/4/5
Interrupt
A
Interrupt
P
149
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