S9S08AW16AE0MFT Freescale Semiconductor, S9S08AW16AE0MFT Datasheet - Page 86

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S9S08AW16AE0MFT

Manufacturer Part Number
S9S08AW16AE0MFT
Description
MCU 16K FLASH AUTO MONET 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets

Specifications of S9S08AW16AE0MFT

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD. POR, PWM, WDT
Number Of I /o
38
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Controller Family/series
HCS08
No. Of I/o's
38
Ram Memory Size
1KB
Cpu Speed
40MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
S08AW
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AW60E
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Height
1 mm
Length
7 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Chapter 6 Parallel Input/Output
Refer to
port E pins as SCI pins.
Refer to
pins as SPI pins.
Refer to
channel pins.
6.3.6
Port F pins are general-purpose I/O pins. Parallel I/O function is controlled by the port F data (PTFD) and
data direction (PTFDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTFPE), slew rate control (PTFSE), and drive strength select (PTFDS) are located in the
high page registers. Refer to
general-purpose I/O control and
Port F general-purpose I/O is shared with TPM1 and TPM2 timer channels. When any of these shared
functions is enabled, the direction, input or output, is controlled by the shared function and not by the data
direction register of the parallel I/O port. Also, for pins which are configured as outputs by the shared
function, the output data is controlled by the shared function and not by the port data register.
Refer to
channel pins.
6.3.7
Port G pins are general-purpose I/O pins. Parallel I/O function is controlled by the port G data (PTGD) and
data direction (PTGDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTGPE), slew rate control (PTGSE), and drive strength select (PTGDS) are located in the
high page registers. Refer to
general-purpose I/O control and
Port G general-purpose I/O is shared with KBI, XTAL, and EXTAL. When a pin is enabled as a KBI input,
the pin functions as an input regardless of the state of the associated PTG data direction register bit. When
the external oscillator is enabled, PTG5 and PTG6 function as oscillator pins. In this case the associated
parallel I/O and pin control registers have no control of the pins.
86
Port F
Port G
Chapter 11, “Serial Communications Interface
Chapter 12, “Serial Peripheral Interface
Chapter 10, “Timer/PWM
Chapter 10, “Timer/PWM
Port F
Port G
MCU Pin:
MCU Pin:
Bit 7
R
Section 6.4, “Parallel I/O
Section 6.4, “Parallel I/O
Bit 7
0
Section 6.5, “Pin
Section 6.5, “Pin
PTF6
MC9S08AC16 Series Data Sheet, Rev. 8
(S08TPMV3)”
(S08TPMV3)” for more information about using port F pins as TPM
EXTAL
6
PTG6/
Figure 6-8. Port G Pin Names
Figure 6-7. Port F Pin Names
6
TPM2CH1
PTF5/
PTG5/
XTAL
5
5
(S08SPIV3)”
Control” for more information about pin control.
Control” for more information about pin control.
for more information about using port E pins as TPM
TPM2CH0
Control” for more information about
Control” for more information about
PTF4/
PTG4/
KBIP4
(S08SCIV4)”
4
4
for more information about using port E
PTG3/
KBIP3
3
R
3
for more information about using
PTG2/
KBIP2
2
R
2
PTG1/
KBIP1
TPM1CH3
Freescale Semiconductor
1
PTF1/
1
PTG0/
KBIP0
Bit 0
TPM1CH2
PTF0/
Bit 0

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