S9S08AW16AE0MFT Freescale Semiconductor, S9S08AW16AE0MFT Datasheet - Page 104

• Manufacturer Part Number: S9S08AW16AE0MFT
• Description: MCU 16K FLASH AUTO MONET 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08AW16AE0MFT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD. POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Controller Family/series: HCS08
• No. Of I/o's: 38
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S08AW
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AW60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Height: 1 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1
Chapter 6 Parallel Input/Output
6.7.13
Port G parallel I/O function is controlled by the registers listed below.
104
Bits 7, 3 and 2 are reserved bits that must always be written to 0.
PTGD[6:0]
PTFDSn
Reset
Reset
6:4, 1:0
Field
Field
6:0
W
W
R
R
Port G I/O Registers (PTGD and PTGDD)
Output Drive Strength Selection for Port F Bits — Each of these control bits selects between low and high
output drive for the associated PTF pin.
0 Low output drive enabled for port F bit n.
1 High output drive enabled for port F bit n.
Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
R
0
0
0
7
7
Figure 6-39. Output Drive Strength Selection for Port F (PTFDS)
PTFDS6
PTGD6
0
0
6
6
Table 6-30. PTFDS Register Field Descriptions
Table 6-31. PTGD Register Field Descriptions
Figure 6-40. Port G Data Register (PTGD)
PTFDS5
MC9S08AC16 Series Data Sheet, Rev. 8
PTGD5
0
0
5
5
PTFDS4
PTGD4
0
0
4
4
Description
Description
PTGD3
R
3
0
3
0
PTGD2
R
0
0
2
2
1
PTFDS1
Freescale Semiconductor
PTGD1
0
0
1
1
PTFDS0
PTGD0
0
0
0
0