MC9S08JM8CLD Freescale Semiconductor, MC9S08JM8CLD Datasheet - Page 325
![MCU 8BIT 8K FLASH 44-LQFP](/photos/37/61/376114/lqfp-44_sml.jpg)
MC9S08JM8CLD
Manufacturer Part Number
MC9S08JM8CLD
Description
MCU 8BIT 8K FLASH 44-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.DEMO9S08JM16.pdf
(386 pages)
Specifications of MC9S08JM8CLD
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Controller Family/series
HCS08
No. Of I/o's
33
Ram Memory Size
1KB
Cpu Speed
48MHz
No. Of Timers
2
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08JM8CLD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 325 of 386
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17.4.8
Interrupts from the INTSTAT register signify events which occur during normal operation
frame tokens (TOKSOF), packet completion (TOKDNE), USB bus reset (USBRST), endpoint errors
(ERROR), suspend and resume (SLEEP and RESUME), and endpoint stalled (STALL).
The ERRSTAT interrupts carry information about specific types of errors, which is needed on an
application specific basis. Using ERRSTAT, an application can determine exactly why a packet transfer
failed
Both registers are maskable via the INTENB and ERRENB registers. The INTSTAT and ERRSTAT are
used to signal interrupts in a two-level structure. Unmasked interrupts from the ERRSTAT register are
reported in the INTSTAT register.
Note that the interrupt registers work in concert with the STAT register. On receipt of an INTSTAT
interrupt, software can check the STAT register and determine which BDT entry was affected by the
transaction.
Freescale Semiconductor
•
•
•
•
—
USB transceiver disabled
USBDP pullup disabled
Endpoints disabled
USB address register set to zero
due to CRC error, PID check error and so on.
Interrupts
MC9S08JM16 Series Data Sheet, Rev. 2
Universal Serial Bus Device Controller (S08USBV1)
—
USB start of
325
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