MC908QB8MDTE Freescale Semiconductor, MC908QB8MDTE Datasheet - Page 165

• Manufacturer Part Number: MC908QB8MDTE
• Description: IC MCU 8BIT 8K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QB8MDTE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Processor Series: HC08QB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 3-Wire, ESCI, SPI, UART
• Number Of Programmable I/os: 13
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Controller Family/series: HC08
• No. Of I/o's: 14
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Digital Ic Case Style: TSSOP
• Rohs Compliant: Yes
• For Use With: DEMO908QB8 - BOARD DEMO FOR MC68HC908QB8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

In this case, an overflow can be missed easily. Because no more SPRF interrupts can be generated until
this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the
SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future
transmissions can set the SPRF bit.
SPSCR read, enable OVRF by setting the ERRIE bit.
Freescale Semiconductor
1
2
3
4
SPI RECEIVE
SPSCR
COMPLETE
OVRF
READ
READ
SPDR
SPRF
BYTE 1 SETS SPRF BIT.
READ SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
READ BYTE 1 IN SPDR,
CLEARING SPRF BIT.
READ SPSCR AGAIN
TO CHECK OVRF BIT.
SPSCR
Figure 15-10. Clearing SPRF When OVRF Interrupt Is Not Enabled
OVRF
READ
READ
SPDR
SPRF
1
2
3
4
BYTE 1
BYTE 1 SETS SPRF BIT.
READ SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
READ BYTE 1 IN SPDR,
CLEARING SPRF BIT.
BYTE 2 SETS SPRF BIT.
BYTE 1
1
1
2
Figure 15-9. Missed Read of Overflow Condition
2
3
3
Figure 15-10
MC68HC908QB8 Data Sheet, Rev. 3
4
BYTE 2
BYTE 2
5
6
7
8
9
4
READ SPSCR AGAIN
TO CHECK OVRF BIT.
5
BYTE 2 SETS SPRF BIT.
READ SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
READ BYTE 2 IN SPDR,
CLEARING SPRF BIT.
illustrates this process. Generally, to avoid this second
BYTE 3
BYTE 3
6
5
5
6
7
8
7
6
READ SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
READ BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
8
7
9
BYTE 4
BYTE 4
10
11
8
12
10
11
12
13
14
READ BYTE 2 SPDR,
CLEARING OVRF BIT.
BYTE 4 SETS SPRF BIT.
READ SPSCR.
READ BYTE 4 IN SPDR,
CLEARING SPRF BIT.
READ SPSCR AGAIN
TO CHECK OVRF BIT.
13
Functional Description
14
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