MC9S08GT8ACFDER Freescale Semiconductor, MC9S08GT8ACFDER Datasheet - Page 72

• Manufacturer Part Number: MC9S08GT8ACFDER
• Description: MCU 8BIT 8K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT8ACFDER

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S08GT
• Core: HCS08
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1
Low-voltage
Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding to
sources that are not active at the time of reset will be cleared.
Any other
Power-on
Resets, Interrupts, and System Configuration
5.7.2
This register includes six read-only status flags to indicate the source of the most recent reset. When a
debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be
set. Writing any value to this register address clears the COP watchdog timer without affecting the contents
of this register. The reset state of these bits depends on what caused the MCU to reset.
72
reset:
reset:
reset:
Field
ILOP
POR
COP
PIN
W
7
6
5
4
R
U = Unaffected by reset
System Reset Status Register (SRS)
POR
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
0 Reset not caused by POR.
1 POR caused reset.
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source may be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
U
1
0
7
Note
PIN
0
0
6
(1)
Writing any value to SIMRS address clears COP watchdog timer.
Figure 5-3. System Reset Status (SRS)
Note
MC9S08GT16A/GT8A Data Sheet, Rev. 1
COP
Table 5-3. SRS Field Descriptions
0
0
5
(1)
Note
ILOP
0
0
4
(1)
Description
ILAD
0
0
0
3
Note
ICG
0
0
2
(1)
Freescale Semiconductor
LVD
1
1
1
0
0
0
0
0
0