MC9S08GT8ACFDER Freescale Semiconductor, MC9S08GT8ACFDER Datasheet - Page 56

• Manufacturer Part Number: MC9S08GT8ACFDER
• Description: MCU 8BIT 8K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT8ACFDER

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S08GT
• Core: HCS08
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory
4.6
The FLASH module has registers in the high-page register space, three locations in the nonvolatile register
space in FLASH memory that are copied into three corresponding high-page control registers at reset.
There is also an 8-byte comparison key in FLASH memory. Refer to
absolute address assignments for all FLASH registers. This section refers to registers and control bits only
by their names. A Freescale-provided equate or header file normally is used to translate these names into
the appropriate absolute addresses.
4.6.1
Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written
only one time. Before any erase or programming operations are possible, write to this register to set the
frequency of the clock for the nonvolatile memory system within acceptable limits.
56
Reset
PRDIV8
DIV[5:0]
DIVLD
Field
7
6
5
W
R
Register Definition
FLASH Clock Divider Register (FCDIV)
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the
internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations.
Program/erase timing pulses are one cycle of this internal FLASH clock, which corresponds to a range of 5 µs
to 6.7 µs. The automated programming logic uses an integer number of these pulses to complete an erase or
program operation. See
DIV5:DIV0 for selected bus frequencies.
0
7
= Unimplemented or Reserved
PRDIV8
if PRDIV8 = 1 — f
if PRDIV8 = 0 — f
0
6
Figure 4-5. FLASH Clock Divider Register (FCDIV)
Equation 4-1
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Table 4-6. FCDIV Field Descriptions
DIV5
0
5
FCLK
FCLK
and
= f
Equation
= f
Bus
DIV4
Bus
0
4
÷ (8 × ([DIV5:DIV0] + 1))
Description
÷ ([DIV5:DIV0] + 1)
4-2.
Table 4-7
DIV3
3
0
shows the appropriate values for PRDIV8 and
Table 4-3
DIV2
0
2
and
Table 4-4
Freescale Semiconductor
DIV1
0
1
for the
Eqn. 4-1
Eqn. 4-2
DIV0
0
0