MC908QY4ACDTER Freescale Semiconductor, MC908QY4ACDTER Datasheet - Page 48
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MC908QY4ACDTER
Manufacturer Part Number
MC908QY4ACDTER
Description
MCU 8BIT 4K FLASH W/ADC 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QT1ACDWE.pdf
(200 pages)
Specifications of MC908QY4ACDTER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-TSSOP
Processor Series
HC08QY
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 48 of 200
- Download datasheet (2Mb)
Analog-to-Digital Converter (ADC10) Module
3.8.3 ADC10 Result Low Register (ADRL)
This register holds the LSBs of the result. This register is updated each time a conversion completes.
Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the result
registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then the
intermediate conversion result will be lost. In 8-bit mode, there is no interlocking with ADRH.
3.8.4 ADC10 Clock Register (ADCLK)
This register selects the clock frequency for the ADC10 and the modes of operation.
ADLPC — ADC10 Low-Power Configuration Bit
48
ADLPC controls the speed and power configuration of the successive approximation converter. This
is used to optimize power consumption when higher sample rates are not required.
1 = Low-power configuration: The power is reduced at the expense of maximum clock speed.
0 = High-speed configuration
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Figure 3-5. ADC10 Data Register High (ADRH), 10-Bit Mode
Figure 3-4. ADC10 Data Register High (ADRH), 8-Bit Mode
ADLPC
Bit 7
Bit 7
Bit 7
AD7
Bit 7
0
0
0
0
0
0
Figure 3-6. ADC10 Data Register Low (ADRL)
Figure 3-7. ADC10 Clock Register (ADCLK)
= Unimplemented
= Unimplemented
= Unimplemented
ADIV1
AD6
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
6
0
0
6
0
0
6
0
6
0
ADIV0
AD5
5
0
0
5
0
0
5
0
5
0
ADICLK
AD4
0
0
0
0
0
0
4
4
4
4
MODE1
AD3
3
0
0
3
0
0
3
0
3
0
MODE0
AD2
2
0
0
2
0
0
2
0
2
0
ADLSMP
AD9
AD1
1
0
0
1
0
1
0
1
0
Freescale Semiconductor
ACLKEN
Bit 0
Bit 0
AD8
Bit 0
Bit 0
AD0
0
0
0
0
0
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