MCHC908QT2MDWER Freescale Semiconductor, MCHC908QT2MDWER Datasheet - Page 30
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MCHC908QT2MDWER
Manufacturer Part Number
MCHC908QT2MDWER
Description
IC MCU 1.5K FLASH W/ADC 8-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QY4MDWER.pdf
(184 pages)
Specifications of MCHC908QT2MDWER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
5
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Processor Series
HC08QT
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
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Memory
30
$003C
$003D
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$0039
$003B
$003E
$003F
Addr.
↓
SIM Reset Status Register
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Status Register 3
ADC Input Clock Register
ADC Status and Control
Break Status Register
Register Name
ADC Data Register
Break Flag Control
Register (ADSCR)
Register (BRKAR)
Register (BFCR)
Unimplemented
Unimplemented
Break Auxiliary
See page 137.
See page 117.
See page 137.
See page 138.
See page 45.
See page 47.
See page 47.
See page 77.
See page 77.
See page 77.
(ADICLK)
Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
(SRSR)
(INT1)
(INT2)
(INT3)
(ADR)
(BSR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
POR:
MC68HC908QY/QT Family Data Sheet, Rev. 6
1. Writing a 0 clears SBSW.
COCO
ADIV2
BCFE
Bit 7
POR
Bit 7
IF14
R
R
R
R
R
R
0
0
1
0
0
0
0
0
0
0
0
= Unimplemented
ADIV1
AIEN
Bit 6
PIN
IF5
R
R
R
R
R
R
6
0
0
0
0
0
0
0
0
0
0
ADCO
ADIV0
COP
Bit 5
IF4
R
R
R
R
R
R
5
0
0
0
0
0
0
0
0
0
0
Indeterminate after reset
ILOP
CH4
Bit 4
IF3
R
R
R
R
R
R
R
4
1
0
0
0
0
0
0
0
0
0
0
= Reserved
ILAD
CH3
Bit 3
R
R
R
R
R
R
3
1
0
0
0
0
0
0
0
0
0
0
0
MODRST
U = Unaffected
CH2
Bit 2
IF1
R
R
R
R
R
R
2
1
0
0
0
0
0
0
0
0
0
0
Freescale Semiconductor
See note 1
SBSW
CH1
Bit 1
LVI
R
R
R
R
R
1
1
0
0
0
0
0
0
0
0
0
0
0
0
BDCOP
Bit 0
CH0
Bit 0
IF15
R
R
R
R
R
R
1
0
0
0
0
0
0
0
0
0
0
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