S9S08SG8E2CTJ Freescale Semiconductor, S9S08SG8E2CTJ Datasheet - Page 244
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S9S08SG8E2CTJ
Manufacturer Part Number
S9S08SG8E2CTJ
Description
MCU 2K FLASH 20-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG4E2CSC.pdf
(316 pages)
Specifications of S9S08SG8E2CTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S08SG8E2CTJ
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
S9S08SG8E2CTJR
Manufacturer:
SAMSUNG
Quantity:
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Chapter 16 Timer/PWM Module (S08TPMV3)
16.3
This section consists of register descriptions in address order. A typical MCU system may contain multiple
TPMs, and each TPM may have one to eight channels, so register names include placeholder characters to
identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer
(TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1.
16.3.1
TPMxSC contains the overflow status flag and control bits used to configure the interrupt enable, TPM
configuration, clock source, and prescale factor. These controls relate to all channels within this timer
module.
244
Reset
CPWMS
Field
TOIE
TOF
W
7
6
5
R
Register Definition
TOF
Timer overflow flag. This read/write flag is set when the TPM counter resets to 0x0000 after reaching the modulo
value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control
register when TOF is set and then writing a logic 0 to TOF. If another TPM overflow occurs before the clearing
sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed
for the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a
previous TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overflow
1 TPM counter has overflowed
Timer overflow interrupt enable. This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is
generated when TOF equals one. Reset clears TOIE.
0 TOF interrupts inhibited (use for software polling)
1 TOF interrupts enabled
Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the
TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconfigures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS.
0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
1 All channels operate in center-aligned PWM mode.
TPM Status and Control Register (TPMxSC)
0
0
7
MSnB:MSnA control bits in each channel’s status and control register.
TOIE
0
6
Figure 16-7. TPM Status and Control Register (TPMxSC)
MC9S08SG8 MCU Series Data Sheet, Rev. 6
Table 16-3. TPMxSC Field Descriptions
CPWMS
5
0
CLKSB
0
4
Description
CLKSA
0
3
PS2
0
2
PS1
Freescale Semiconductor
1
0
PS0
0
0
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