S9S08SG8E2CTJ Freescale Semiconductor, S9S08SG8E2CTJ Datasheet - Page 162
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S9S08SG8E2CTJ
Manufacturer Part Number
S9S08SG8E2CTJ
Description
MCU 2K FLASH 20-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG4E2CSC.pdf
(316 pages)
Specifications of S9S08SG8E2CTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S08SG8E2CTJ
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
S9S08SG8E2CTJR
Manufacturer:
SAMSUNG
Quantity:
400 000
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Chapter 11 Inter-Integrated Circuit (S08IICV2)
11.1.4
Figure 11-2
11.2
This section describes each user-accessible pin signal.
11.2.1
The bidirectional SCL is the serial clock line of the IIC system.
11.2.2
The bidirectional SDA is the serial data line of the IIC system.
11.3
This section consists of the IIC register descriptions in address order.
162
External Signal Description
Register Definition
Block Diagram
SCL — Serial Clock Line
SDA — Serial Data Line
is a block diagram of the IIC.
CTRL_REG
ADDR_DECODE
Control
Address
Clock
Input
Sync
Figure 11-2. IIC Functional Block Diagram
MC9S08SG8 MCU Series Data Sheet, Rev. 6
FREQ_REG
SCL
Arbitration
ADDR_REG
Control
Start
Stop
SDA
STATUS_REG
Interrupt
Compare
Register
Address
In/Out
Data
Shift
DATA_MUX
DATA_REG
Data Bus
Freescale Semiconductor
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