S9S08SG4E2VTG Freescale Semiconductor, S9S08SG4E2VTG Datasheet - Page 75

• Manufacturer Part Number: S9S08SG4E2VTG
• Description: MCU 4K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08SG4E2VTG

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 16-TSSOP
• Processor Series: S08SG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• On-chip Dac: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1
2
6.3
The MC9S08SG8 Series devices contain a feature that allows for up to eight port pins to be tied together
externally to allow higher output current drive. The ganged output drive control register (GNGC) is a
write-once register that is used to enabled the ganged output feature and select which port pins will be used
as ganged outputs. The GNGEN bit in GNGC enables ganged output. The GNGPS[7:1] bits are used to
select which pin will be part of the ganged output.
When GNGEN is set, any pin that is enabled as a ganged output will be automatically configured as an
output and follow the data, drive strength and slew rate control of PTC0. The ganged output drive pin
mapping is shown in
Freescale Semiconductor
Drive Strength
Data Direction
Ganged output not available on 8-pin packages. PTC3-PTC0 not available on 16-pin packages, however PTC0 control
registers are still used to control ganged output.
When GNGEN = 1, PTC0 is forced to an output, regardless of the value in PTCDD0 in PTCDD.
Slew Rate
Port Pin
Control
Control
Control
Control
Data
Ganged Output
2
See the DC characteristics in the electrical section for maximum Port I/O
currents allowed for this MCU.
When a pin is enabled as ganged output, this feature will have priority over
any digital module. An enabled analog function will have priority over the
ganged output pin. See
GNGPS7
PTB5
Table
6-1.
Pin is automatically configured as output when pin is enabled as ganged output.
GNGPS6
PTB4
MC9S08SG8 MCU Series Data Sheet, Rev. 6
Table 6-1. Ganged Output Pin Enable
Table 2-1
PTCDS0 in PTCDS controls drive strength of output
GNGPS5
PTCSE0 in PTCSE controls slew rate of output
PTB3
PTCD0 in PTCD controls data value of output
for information on pin priority.
NOTE
GNGPS4
GNGC Register Bits
PTB2
GNGPS3
PTC3
GNGPS2
Chapter 6 Parallel Input/Output Control
PTC2
GNGPS1
PTC1
GNGEN
PTC0
1
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