MC9S08QG84CFQE Freescale Semiconductor, MC9S08QG84CFQE Datasheet - Page 78

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MC9S08QG84CFQE

Manufacturer Part Number
MC9S08QG84CFQE
Description
IC MCU 8BIT B54 RATING 8-DFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08QG84CFQE

Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
4
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
1
Chapter 5 Resets, Interrupts, and General System Control
5.8.10
This high page register is used to report the status of the low voltage warning function and to select the
low voltage detect trip voltage.
Any other
76
LVWF will be set in the case when V
LVWACK
reset:
POR:
LVWF
LVWV
LVD:
Field
LVDV
7
6
5
4
W
R
LVWF
System Power Management Status and Control 3 Register
(SPMSC3)
Figure 5-12. System Power Management Status and Control 3 Register (SPMSC3)
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
Low-Voltage Warning Acknowledge — The LVWF bit indicates the low voltage warning status. Writing a 1 to
LVWACK clears LVWF to a 0 if a low voltage warning is not present.
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V
0 Low trip point selected (V
1 High trip point selected (V
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V
0 Low trip point selected (V
1 High trip point selected (V
0
0
0
7
1
1
1
= Unimplemented or Reserved
LVWACK
0
0
0
0
6
Table 5-14. SPMSC3 Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Supply
LVD
LVW
LVDV
LVD
LVW
transitions below the trip point or after reset and V
U
U
0
5
= V
= V
= V
= V
LVDL
LVWL
LVDH
LVWH
).
).
).
).
LVWV
U
U
0
4
Description
3
0
0
0
0
U= Unaffected by reset
0
0
0
0
2
Supply
is already below V
Freescale Semiconductor
0
0
0
0
LVD
1
LVW
).
).
0
0
0
0
LVW
0
.

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