MC9S08QG84CFQE Freescale Semiconductor, MC9S08QG84CFQE Datasheet - Page 151

• Manufacturer Part Number: MC9S08QG84CFQE
• Description: IC MCU 8BIT B54 RATING 8-DFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG84CFQE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• For Use With: DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.3.3
10.3.4
Freescale Semiconductor
CLKST
FTRIM
Field
TRIM
Field
7:0
3:2
1
0
Reset:
Reset:
POR:
POR:
W
W
R
R
ICS Trim Register (ICSTRM)
ICS Status and Control (ICSSC)
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00
01
11
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared.
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
Output of FLL is selected.
FLL Bypassed, Internal reference clock is selected.10FLL Bypassed, External reference clock is selected.
Reserved.
U
1
7
7
0
0
0
Table 10-4. ICS Status and Control Register Field Descriptions
Figure 10-6. ICS Status and Control Register (ICSSC)
Table 10-3. ICS Trim Register Field Descriptions
U
0
0
0
0
6
6
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Figure 10-5. ICS Trim Register (ICSTRM)
U
0
0
0
0
5
5
U
0
0
0
0
4
4
Description
Description
TRIM
U
0
0
0
3
3
CLKST
U
0
0
0
2
2
Internal Clock Source (S08ICSV1)
OSCINIT
U
0
0
0
1
1
FTRIM
U
U
0
0
0
0
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