ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet - Page 60
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ST10F276Z5T3
Manufacturer Part Number
ST10F276Z5T3
Description
MCU 16BIT 832KBIT FLASH 144-TQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F276Z5T3.pdf
(239 pages)
Specifications of ST10F276Z5T3
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
832KB (832K x 8)
Program Memory Type
FLASH
Ram Size
68K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-TQFP, 144-VQFP
Cpu Family
ST10
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C
Total Internal Ram Size
68KB
# I/os (max)
111
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
24-chx10-bit
Instruction Set Architecture
CISC/RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Processor Series
ST10F27x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
68 KB
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
For Use With
497-6399 - KIT DEV STARTER ST10F276Z5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F276Z5T3
Manufacturer:
STMicroelectronics
Quantity:
10 000
Bootstrap loader
5.4.3
5.4.4
60/239
ST10 configuration in CAN BSL
When the ST10F276Z5 enters BSL mode via CAN, the configuration shown in
automatically set (values that deviate from the normal reset values are marked in bold).
Table 32.
1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin
2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low
Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading
sequence is not time limited. Pin CAN1_TxD1 is configured as output, so the ST10F276Z5
can return the identification frame. Even if the internal IFLASH is enabled, a code cannot be
executed from it.
Loading the start-up code via CAN
After sending the acknowledge byte, the BSL enters a loop to receive 128 bytes via CAN1.
Hint: The number of bytes loaded when booting via the CAN interface has been extended to
128 bytes to allow the reconfiguration of the CAN Bit Timing Register with the best timings
(synchronization window, ...). This can be achieved by the following sequence of
instructions:
ReconfigureBaud rate:
These 128 bytes are stored sequentially into locations 00’FA40
IRAM, allowing up to 64 instructions to be placed into the RAM area. To execute the loaded
code the BSL then jumps to location 00’FA40
bootstrap loading sequence is now terminated; however, the ST10F276Z5 remains in BSL
Watchdog timer
Register SYSCON
Context pointer CP
Register STKUN
Stack pointer SP
Register STKOV
Register BUSCON0
CAN1 Status/Control register 0000
CAN1 Bit timing register
XPERCON
P4.6 / CAN1_TxD
DP4.6
level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration.
during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE
signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.
MOV R1,#041h
MOV DPP3:0EF00h,R1 ; Put CAN in Init, enable Configuration Change
MOV R1,#01600h
MOV DPP3:0EF06h,R1 ; 1MBaud at Fcpu = 20 MHz
Function or register
ST10 configuration in CAN BSL
Disabled
0404
FA00
FA00
FA40
FC00
access to startup
configuration
access to ‘0’ frame
042D
‘1’
‘1’
H
H
H
H
H
H
H
Access
(1)
(2)
H
, that is, the first loaded instruction. The
XPEN bit set
Initialized only if Bootstrap via CAN
Initialized only if Bootstrap via CAN
XRAM1-2, XFlash, CAN1 and XMISC enabled
Initialized only if Bootstrap via CAN
Initialized only if Bootstrap via CAN
H
through 00’FABF
Notes
ST10F276Z5
Table 32
H
of the
is