ST10F269-DP STMicroelectronics, ST10F269-DP Datasheet - Page 47

• Manufacturer Part Number: ST10F269-DP
• Description: MCU 16BIT 256K FLASH 144PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269-DP

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BFQFP
• Processor Series: ST10F26x
• Core: ST10
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

xxIC (yyyyh / zzh)
8.4 - Exception and Error Traps List
Table 8 shows all of the possible exceptions or error conditions that can arise during run-time :
Table 8 : Trap Priorities
*
Reset Functions:
Class A Hardware Traps:
Class B Hardware Traps:
Reserved
Software Traps
15
- All the class B traps have the same trap number (and vector) and the same lower priority compare to the class A traps and to the resets.
- Each class A traps has a dedicated trap number (and vector). They are prioritized in the second priority level.
- The resets have the highest priority level and the same trap number.
- The PSW.ILVL CPU priority is forced to the highest level (15) when these exeptions are serviced.
-
GLVL
ILVL
xxIR
xxIE
Bit
14
-
Exception Condition
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Undefined Opcode
Protected Instruction Fault
Illegal word Operand Access
Illegal Instruction Access
Illegal External Bus Access
TRAP Instruction
Hardware Reset
Software Reset
Watchdog Timer Overflow
13
-
Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
Interrupt Priority Level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
Interrupt Enable Control Bit (individually enables/disables a specific source)
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
12
-
11
-
10
-
UNDOPC
PRTFLT
ILLBUS
ILLOPA
STKOF
STKUF
ILLINA
9
-
Trap
Flag
NMI
SFR Area
8
-
STUTRAP
STOTRAP
NMITRAP
RESET
RESET
RESET
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
xxIR
Vector
RW
Trap
7
Function
xxIE
RW
6
[002Ch - 003Ch]
0000h – 01FCh
in steps of 4h
Location
00’0000h
00’0000h
00’0000h
00’0008h
00’0010h
00’0018h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
5
Vector
Any
4
ILVL
RW
3
[0Bh - 0Fh]
[00h - 7Fh]
Number
Reset Value: - - 00h
Trap
0Ah
0Ah
0Ah
0Ah
0Ah
00h
00h
00h
02h
04h
06h
Any
2
ST10F269
1
GLVL
Priority
Current
Priority
RW
Trap*
CPU
III
III
III
II
II
II
47/160
I
I
I
I
I
0