ST10F269-DP STMicroelectronics, ST10F269-DP Datasheet - Page 136

• Manufacturer Part Number: ST10F269-DP
• Description: MCU 16BIT 256K FLASH 144PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269-DP

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BFQFP
• Processor Series: ST10F26x
• Core: ST10
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F269
21.4 - AC characteristics
21.4.1 - Test Waveforms
Figure 65 : Input / Output Waveforms
Figure 66 : Float Waveforms
21.4.2 - Definition of Internal Timing
The internal operation of the ST10F269 is
controlled by the internal CPU clock f
edges of the CPU clock can trigger internal (for
example pipeline) or external (for example bus
cycles) operations.
The specification of the external timing (AC
Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock,
called “TCL”.
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For timing purposes a port pin is no longer floating when V
It begins to float when a 100mV change from the loaded V
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.
Timing measurements are made at V
0.45V
2.4V
V
Load
V
V
Load
Load
+0.1V
-0.1V
0.2V
0.2V
DD
DD
CPU
IH
+0.9
-0.1
. Both
Test Points
min for a logic ‘1’ and V
Reference
Timing
Points
V
V
OL
OH
0.2V
0.2V
The CPU clock signal can be generated by
different mechanisms. The duration of TCL and its
variation (and also the derived external timing)
depends on the mechanism used to generate
f
This influence must be regarded when calculating
the timings for the ST10F269.
The example for PLL operation shown in Figure
67 refers to a PLL factor of 4.
CPU
DD
DD
.
-0.1
+0.9
OH
LOAD
/V
OL
IL
changes of ±100mV.
max for a logic ‘0’.
level occurs (I
V
V
OL
OH
OH
+0.1V
-0.1V
/I
OL
= 20mA).