F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 76

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

CAN modules
17
Note:
17.1
17.2
76/182
CAN modules
The two integrated CAN modules (CAN1 and CAN2) are identical and handle the
completely autonomous transmission and reception of CAN frames according to the CAN
specification V2.0 part B (active). It is based on the C-CAN specification.
Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers
as well as extended frames with 29-bit identifiers.
Because of duplication of the CAN controllers, the following adjustments are to be
considered:
●
●
●
●
●
●
If one or both CAN modules is used, Port 4 cannot be programmed to output all 8 segment
address lines. Thus, only four segment address lines can be used, reducing the external
memory space to 5 Mbytes (1 Mbyte per CS line).
Configuration support
It is possible that both CAN controllers are working on the same CAN bus, supporting
together up to 64 message objects. In this configuration, both receive signals and both
transmit signals are linked together when using the same CAN transceiver. This
configuration is especially supported by providing open drain outputs for the CAN1_Txd and
CAN2_TxD signals. The open drain function is controlled with the ODP4 register for port P4:
in this way it is possible to connect together P4.4 with P4.5 (receive lines) and P4.6 with
P4.7 (transmit lines configured to be configured as Open-Drain).
The user is also allowed to map internally both CAN modules on the same pins P4.5 and
P4.6. In this way, P4.4 and P4.7 may be used either as general purpose I/O lines, or used
for I
register it is necessary to set bit XMISCEN of XPERCON register and bit XPEN of SYSCON
register.
CAN bus configurations
Depending on application, CAN bus configuration may be one single bus with a single or
multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F272 is
able to support these two cases.
2
Same internal register addresses of both CAN controllers, but with base addresses
differing in address bit A8; separate chip select for each CAN module. Refer to
Chapter 4: Memory organization on page
The CAN1 transmit line (CAN1_TxD) is the alternate function of the Port P4.6 pin and
the receive line (CAN1_RxD) is the alternate function of the Port P4.5 pin.
The CAN2 transmit line (CAN2_TxD) is the alternate function of the Port P4.7 pin and
the receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin.
Interrupt request lines of the CAN1 and CAN2 modules are connected to the XBUS
interrupt lines together with other X-Peripherals sharing the four vectors.
The CAN modules must be selected with corresponding CANxEN bit of XPERCON
register before the bit XPEN of SYSCON register is set.
The reset default configuration is: CAN1 enabled, CAN2 disabled.
C interface. This is possible by setting bit CANPAR of XMISC register. To access this
23.
ST10F272B/ST10F272E