STM32F101ZDT6 STMicroelectronics, STM32F101ZDT6 Datasheet - Page 104
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STM32F101ZDT6
Manufacturer Part Number
STM32F101ZDT6
Description
MCU ARM 32BIT 384K FLASH 144LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F101RET6.pdf
(106 pages)
Specifications of STM32F101ZDT6
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
36MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
112
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
STM32F101x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
48 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
112
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
On-chip Dac
12 bit, 2 Channel
Featured Product
STM32 Cortex-M3 Companion Products
Eeprom Size
-
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F101ZDT6
Manufacturer:
STM
Quantity:
243
Company:
Part Number:
STM32F101ZDT6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Revision history
104/106
Table 65.
30-Mar-2009
Date
Document revision history (continued)
Revision
5
I/O information clarified
corrected in
STM32F101xE features and peripheral
In
– I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15
– PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
PG14 pin description modified in
Figure 6: Memory map on page 33
Note modified in
code with data processing running from Flash
current consumption in Sleep mode, code running from Flash or
Figure
changed).
Table 21: High-speed external user clock characteristics
Low-speed user external clock characteristics
ACC
FSMC configuration modified for
Notes modified below
SRAM/PSRAM/NOR read waveforms
non-multiplexed SRAM/PSRAM/NOR write
t
SRAM/PSRAM/NOR read timings
multiplexed NOR/PSRAM write
Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
timings.
In
Table 38: Synchronous non-multiplexed PSRAM write
– t
– t
– t
Figure 25: Synchronous multiplexed NOR/PSRAM read
Figure 26: Synchronous multiplexed PSRAM write timings
Figure 28: Synchronous non-multiplexed PSRAM write timings
modified. Small text changes.
w(NADV)
updated
column to Remap column.
Table 5: High-density STM32F101xx pin
Table 36: Synchronous multiplexed PSRAM write timings
v(Data-CLK)
d(CLKL-Data)
h(CLKL-DV)
Doc ID 14610 Rev 7
HSI
14,
max values modified in
values modified in
Figure 15
Table 2: STM32F101xC, STM32F101xD and
/ t
renamed as t
min value removed and max value added
h(CLKL-ADV)
Table 14: Maximum current consumption in Run mode,
STM32F101xC, STM32F101xD, STM32F101xE
and
Figure 21: Asynchronous non-multiplexed
on page
Figure 16
removed
d(CLKL-Data)
Table 31: Asynchronous non-multiplexed
Changes
timings. t
Table 25: HSI oscillator characteristics
Asynchronous waveforms and
1. Number of ADC peripherals
Table 6: FSMC pin
and
modified.
show typical curves (titles
and
Table 34: Asynchronous
counts.
h(Data_NWE)
Figure 22: Asynchronous
definitions:
waveforms.
modified.
and
Table 16: Maximum
definition.
modified in
timings:
timings,
and
and
and
Table 22:
timings.
RAM.