STM32F105R8T6 STMicroelectronics, STM32F105R8T6 Datasheet - Page 20

MCU ARM 64KB FLASH MEM 64-LQFP

STM32F105R8T6

Manufacturer Part Number
STM32F105R8T6
Description
MCU ARM 64KB FLASH MEM 64-LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheets

Specifications of STM32F105R8T6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB OTG
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
51
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
STM32F105x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
20 KB
Interface Type
CAN, I2C, SPI, USART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
51
Number Of Timers
10
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit x 2, 16 Channel
On-chip Dac
12 bit x 2, 2 Channel
Cpu Family
STM32
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
20KB
# I/os (max)
51
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LQFP
For Use With
497-10591 - DAUGHTER BOARD FOR STM32497-9040 - DEV KIT FOR STM32497-9041 - DEV KIT FOR STM32497-9042 - DEV KIT FOR STM32497-9043 - DEV KIT FOR STM32497-8924 - EVAL BOARD FOR STM32F107VCT497-8853 - BOARD DEMO STM32 UNIV USB-UUSCI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-8922

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Description
2.3.21
2.3.22
2.3.23
20/101
Controller area network (CAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to
1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total)
are not shared with any other peripheral.
Universal serial bus on-the-go full-speed (USB OTG FS)
The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG full-
speed (12 Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG FS
peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It
has software-configurable endpoint setting and supports suspend/resume. The USB OTG
full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL
connected to the HSE oscillator. The major features are:
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
I/Os on APB2 with up to 18 MHz toggling speed
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and group
addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive
FIFO are both 2 Kbytes, that is 4 Kbytes in total
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 with
the timestamp comparator connected to the TIM2 trigger input
Triggers interrupt when system time becomes greater than target time
1.25 KB of SRAM used exclusively by the endpoints (not shared with any other
peripheral)
4 bidirectional endpoints
HNP/SNP/IP inside (no need for any external resistor)
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
the SOF output can be used to synchronize the external audio DAC clock in
isochronous mode
in accordance with the USB 2.0 Specification, the supported transfer speeds are:
in Host mode: full speed and low speed
in Device mode: full speed
Doc ID 15274 Rev 5
STM32F105xx, STM32F107xx

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