Z86E7216PSG Zilog, Z86E7216PSG Datasheet - Page 30

• Manufacturer Part Number: Z86E7216PSG
• Description: IC 16K OTP ZIRC 40-DIP
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E7216PSG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 16MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 31
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 748 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.620", 15.75mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Z86E72/73
OTP Microcontroller
26
dictated by the I/O direction to Port 0 of the upper nibble P07–P04. The lower nib-
ble must have the same direction as the upper nibble.
For external memory references, Port 0 can provide address bits A11–A8 (lower
nibble) or A15–A8 (lower and upper nibble) depending on the required address
space. If the address range requires 12 bits or less, the upper nibble of Port 0 can
be programmed independently as I/O while the lower nibble is used for address-
ing. If one or both nibbles are needed for I/O operation, they must be configured
by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured
as an input port.
Port 0 is set in the High-Impedance Mode if selected as an address output state
along with Port 1 and the control signals /AS, /DS, and R//W.
A software option is available to program 0.4 V
CMOS trip inputs on P00–P03.
DD
This allows direct interface to mouse/trackball IR sensors.
Ω
±
An optional 200
50% K
resistive transistor pull-up is available as a software
option of all Port 0 bits with nibble select.
These pull-ups are disabled when configured (bit by bit) as an output. See
Figure
14.
PS008704-0507