STM32F103R8H7 STMicroelectronics, STM32F103R8H7 Datasheet - Page 69

• Manufacturer Part Number: STM32F103R8H7
• Description: MCU 32BIT 64K FLASH 64BGA
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F103R8H7

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 51
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LFBGA
• Processor Series: STM32F103x
• Core: ARM Cortex M3
• 3rd Party Development Tools: EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ST-LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

STM32F103x8, STM32F103xB
SPI interface characteristics
Unless otherwise specified, the parameters given in
performed under the ambient temperature, f
conditions summarized in
Refer to
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 42.
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
DuCy(SCK)
t
t
t
t
dis(SO)
t
w(SCKH)
t
w(SCKL)
a(SO)
1/t
su(NSS)
t
Symbol
t
t
t
h(NSS)
t
t
t
su(MI)
t
v(SO)
v(MO)
h(MO)
su(SI)
h(SO)
t
h(MI)
t
the data.
the data in Hi-Z
h(SI)
r(SCK)
f(SCK)
f
c(SCK)
SCK
(1)(2)
(1)
(1)(3)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Section 5.3.12: I/O current injection characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock
duty cycle
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access
time
Data output disable
time
Data output valid time Slave mode (after enable edge)
Data output valid time Master mode (after enable edge)
Data output hold time
SPI characteristics
Parameter
Table
Doc ID 13587 Rev 13
9.
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
PCLKx
Conditions
PCLK
PCLK
frequency and V
= 20 MHz
= 36 MHz,
Table 42
for more details on the
are derived from tests
Electrical characteristics
DD
4t
2t
Min
PCLK
PCLK
30
15
supply voltage
50
5
5
5
4
2
2
0
3t
Max
PCLK
18
70
60
10
25
18
5
8
MHz
Unit
69/99
ns
ns
%