ST10R172LT1 STMicroelectronics, ST10R172LT1 Datasheet - Page 67

• Manufacturer Part Number: ST10R172LT1
• Description: MCU 16BIT ROMLESS LV 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R172LT1

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: ST10
• No. Of I/o's: 77
• Ram Memory Size: 1KB
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Embedded Interface Type: SPI, USART
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST10R1x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: In Transition

1
2
3
The transition of shift and latch edge of SSPCLK is programmable. This figure uses the
falling edge as shift edge (drawn bold).
The bit timing is repeated for all bits to be transmitted or received.
The active level of the chip enable lines is programmable. This figure uses an active low
CE (drawn bold). At the end of a transmission or reception the CE signal is disabled in sin-
gle transfer mode. In continuous transfer mode it remains active.
SSPDAT
SSPCLK
SSPDAT
SSPCEx
SSPCLK
SSPCEx
1)
1)
t
205
t
last Wr. Bit
207
t
200
t
209
1st Bit
t
210
Figure 26 SSP write timing
Figure 27 SSP read timing
t
t
202
207
t
203
2nd Bit
ST10R172L - ELECTRICAL CHARACTERISTICS
t
201
1st.In Bit
t
211
t
204
t
208
2)
2)
Lst.In Bit
t
207
t
212
Last Bit
t
206
t
209
t
206
3)
3)
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1