ST10R172LT1 STMicroelectronics, ST10R172LT1 Datasheet - Page 38

• Manufacturer Part Number: ST10R172LT1
• Description: MCU 16BIT ROMLESS LV 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R172LT1

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: ST10
• No. Of I/o's: 77
• Ram Memory Size: 1KB
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Embedded Interface Type: SPI, USART
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST10R1x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: In Transition

ST10R172L - ELECTRICAL CHARACTERISTICS
15.3.1 Cpu Clock Generation Mechanisms
ST10R172L internal operation is controlled by the CPU clock f
clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The external
timing (AC Characteristics) specification therefore depends on the time between two consec-
utive edges of the CPU clock, called “TCL” (see figure below).
The CPU clock signal can be generated by different mechanisms. The duration of TCLs and
their variation (and also the external timing) depends on the f
must be considered when calculating ST10R172L timing.
The CPU clock generation mechanism is set during reset by the logic levels on pins P0.15-13
(P0H.7-5).
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1
P0.15-13 (P0H.7-5)
1
1
1
Phase Locked Loop Operation (PLL factor=4)
Direct Clock Drive
Prescaler Operation
1
1
0
f
f
f
f
f
f
XTAL
CPU
XTAL
CPU
XTAL
CPU
1
0
1
Figure 11 CPU clock generation mechanisms
Table 12 CPU clock generation mechanisms
CPU frequency
f
F
F
F
CPU
XTAL
XTAL
XTAL
= f
* 4
* 3
* 2
XTAL
* F
External clock
input range 10-
50MHz
2.5 to 12.5 MHz
3.33 to 16.66 MHz
5 to 25 MHz
CPU
CPU
generation mechanism. This
TCL
Notes
Default configuration
. Both edges of the CPU
TCL
TCL TCL
TCL TCL