Z86C9620VSG Zilog, Z86C9620VSG Datasheet - Page 38

• Manufacturer Part Number: Z86C9620VSG
• Description: IC Z8 20MHZ C91 W/7 PORTS 68PLCC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86C9620VSG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, UART/USART
• Number Of I /o: 52
• Program Memory Type: ROMless
• Ram Size: 236 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Processor Series: Z86C9xx
• Core: Z8
• Data Bus Width: 8 bit
• Program Memory Size: 16 KB
• Data Ram Size: 236 B
• Interface Type: UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Peripherals: -
• Lead Free Status / Rohs Status: Details

Z86C61/62/96
CMOS Z8 Microcontroller
Z8 EXPANDED REGISTER FILE CONTROL REGISTERS
38
*Default Value After RESET
P4M (FH) 03H
P5D (FH) 05H
D7 D6
D7 D6 D5 D4 D3 D2 D1 D0
P4 (FH) 02H
P5 (FH) 04H
D7 D6
D7 D6
D5 D4 D3 D2 D1
Figure 45. Port 4 Mode Register
Figure 47. Port 5 Mode Register
Figure 44. Port 4 Data Register
Figure 46. Port 5 Data Register
D5 D4 D3 D2 D1
D5 D4 D3 D2 D1
(F( 03: (Write Only)
(f) 04: (Read/Write)
(F) 05: (Write Only)
(F) 02: Read/Write)
D0
D0
D0
P40 - P47 I/O Definition
P50 - P57 I/O Definition
0
1
0
1
Data
0
1
Data
0
1
Defines Bit as Output
Defines Bit as Input
Defines Bit as Output
Defines Bit as Input*
Defines Level 0
Defines Level 1
Defines Level 0
Defines Level 1
PS003501-0301
P R E L I M I N A R Y
*Default Value After RESET
P6D (FH) 08H
*Default Value After RESET
P45M (FH) 06H
P6 (FH) 07H
P6M (FH) 09H
*Default Value After RESET
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 48. Port 4/5 Configuration Register
Figure 50. Port 6 Mode Register
Figure 51. Port 6 Mode Register
Figure 49. Port 6 Data Register
D4
D3 D2 D1 D0
(F) 07: (Read/Write)
(F) 06: (Write Only)
(F) 08: (Write Only)
(F) 09: (Write Only)
D0
P60 - P63 I/O Definition
Reserved (Must be 0)
0
1
0
1
0 Port 4 Open-drain*
1 Port 4 Push-pull
Reserved (Must be 0)
0 Port 5 Open-drain*
1 Port 5 Push-pull
Reserved (Must be 0)
Data
0
1
Reserved (Must be 0)
Defines Bit as Output
Defines Bit as Input*
Port 6 Open-drain*
Port 6 Push-pull
Defines Level 0
Defines Level 1
DS97Z8X1600
Zilog