ST10R272LT1/TR STMicroelectronics, ST10R272LT1/TR Datasheet - Page 54

MCU 16BIT ROMLESS LV 100-TQFP

ST10R272LT1/TR

Manufacturer Part Number
ST10R272LT1/TR
Description
MCU 16BIT ROMLESS LV 100-TQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10R272LT1/TR

Core Processor
ST10
Core Size
16-Bit
Speed
50MHz
Connectivity
EBI/EMI, SSP, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
77
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
ST10R2x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
SSP, USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
77
Number Of Timers
5
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST10R272LT1/TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST10R272LT1/TR
Manufacturer:
ST
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ST10R272L - ELECTRICAL CHARACTERISTICS
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1
Parameter
RdCS to Valid Data In
(with RW delay)
RdCS to Valid Data In
(no RW delay)
RdCS, WrCS Low Time
(with RW delay)
RdCS, WrCS Low Time
(no RW delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
Address hold after
RdCS, WrCS
Data hold after WrCS
1) Output loading is specified using Figure 13 (CL = 5 pF).
2) This delay assumes that the following bus cycle is a multiplexed bus cycle. If next bus cycle
is demultiplexed, refer to demuxultiplexed equivalent AC timing.
1 2
Symbol
t
t
t
t
t
t
t
t
t
46
47
48
49
50
51
52
54
56
SR –
SR –
CC 13 +
CC 23 +
CC 10 +
SR 0
SR –
CC 10 +
CC 10 +
Table 17 Multiplexed bus
Max. CPU Clock
= 50 MHz
min.
t
t
t
t
t
C
C
C
F
F
max.
3 +
13 +
13 +
t
C
t
t
C
F
2
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
2TCL - 7+
3TCL - 7+
2TCL - 10 +
0
2TCL - 10 +
2TCL - 10 +
t
t
C
C
t
t
t
C
F
F
max.
2TCL - 17
+
3TCL - 17
+
2TCL - 7 +
t
t
C
C
t
F
2
ns
ns
ns
ns
ns
ns
ns
ns
ns

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