EZ80F92AZ020EC00TR Zilog, EZ80F92AZ020EC00TR Datasheet - Page 176
EZ80F92AZ020EC00TR
Manufacturer Part Number
EZ80F92AZ020EC00TR
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020EC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F92AZ020EC00T
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eZ80F92/eZ80F93
Product Specification
169
Because many register Read/Write operations exhibit secondary effects, such as clearing
flags or causing operations to commence, the effects of the Read/Write operations during a
ZDI BREAK must be taken into consideration.
Bus Requests During ZDI DEBUG Mode
The ZDI block on the eZ80F92 device allows an external device to take control of the
address and data bus while the eZ80F92 device is in DEBUG mode. ZDI_BUSACK_EN
causes ZDI to allow or prevent acknowledgement of bus requests by external peripherals.
The bus acknowledge only occurs at the end of the current ZDI operation (indicated by a
High during the single-bit byte separator). The default reset condition is for bus acknowl-
edgement to be disabled. To allow bus acknowledgement, the ZDI_BUSACK_EN must be
written.
When an external bus request (BUSREQ pin asserted) is detected, ZDI waits until comple-
tion of the current operation before responding. ZDI acknowledges the bus request by
asserting the bus acknowledge (BUSACK) signal. If the ZDI block is not currently shift-
ing data, it acknowledges the bus request immediately. ZDI uses the single-bit byte separa-
tor of each data word to determine if it is at the end of a ZDI operation. If the bit is a
logical 0, ZDI does not assert BUSACK to allow additional data Read or Write operations.
If the bit is a logical 1, indicating completion of the ZDI commands, BUSACK is asserted.
Potential Hazards of Enabling Bus Requests During DEBUG Mode
There are some potential hazards that the user must be aware of when enabling external
bus requests during ZDI DEBUG mode. First, when the address and data bus are used by
an external source, ZDI must only access ZDI registers and internal CPU registers to pre-
vent possible Bus contention. The bus acknowledge status is reported in the
ZDI_BUS_STAT register. The BUSACK output pin also indicates the bus acknowledge
state.
A second hazard is that when a bus acknowledge is granted, the ZDI is subject to any
WAIT states that are assigned to the device currently accessed by the external peripheral.
To prevent data errors, ZDI should avoid data transmission while another device is con-
trolling the bus.
Finally, exiting ZDI DEBUG mode while an external peripheral controls the address and
data buses, as indicated by BUSACK assertion, may produce unpredictable results.
PS015313-0508
Zilog Debug Interface
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