Z8F0822PJ020EG Zilog, Z8F0822PJ020EG Datasheet - Page 141

• Manufacturer Part Number: Z8F0822PJ020EG
• Description: IC ENCORE MCU FLASH 8K 28DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0822PJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z8F082xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4207; Z8F0822PJ020EG

Operation
PS022517-0508
SDA and SCL Signals
I
2
C Interrupts
The I
master is supported. Arbitration between two masters must be accomplished in software.
I
•
•
•
•
I
bit first. SCL is the common clock for the I
alternate functions are selected for their respective GPIO ports, the pins are automatically
configured for open-drain operation.
The master (I
becomes skewed by a slow slave device. During the low period of the clock, the slave
pulls the SCL signal Low to suspend the transaction. The master releases the clock at the
end of the low period and notices that the clock remains low instead of returning to a high
level. When the slave releases the clock, the I
data is transferred in bytes and there is no limit to the amount of data transferred in one
operation. When transmitting data or acknowledging read data from the slave, the SDA
signal changes in the middle of the low period of SCL and is sampled in the middle of the
high period of SCL.
The I
edge, and Baud Rate Generator. These four interrupt sources are combined into a single
interrupt request signal to the interrupt controller. The Transmit Interrupt is enabled by the
IEN and TXI bits of the control register. The Receive and Not Acknowledge interrupts are
enabled by the IEN bit of the control register. BRG interrupt is enabled by the BIRQ and
IEN bits of the control register.
Not Acknowledge interrupts occur when a Not Acknowledge condition is received from
the slave or sent by the I
Acknowledge event sets the NCKI bit of the I
by setting the
the I
action. In an ISR, the NCKI bit should always be checked prior to servicing transmit or
receive interrupt conditions because it indicates the transaction is being terminated.
2
2
C supports the following operations:
C sends all addresses, data and acknowledge signals over the SDA line, most-significant
Master transmits to a 7-bit Slave
Master transmits to a 10-bit Slave
Master receives from a 7-bit Slave
Master receives from a 10-bit Slave
2
2
2
C Controller waits until either the STOP or START bit is set before performing any
C Controller operates in MASTER mode to transmit and receive data. Only a single
C Controller contains four sources of interrupts—Transmit, Receive, Not Acknowl-
2
START
C) is responsible for driving the SCL clock signal, although the clock signal
or
STOP
2
C Controller and neither the
bit in the I
2
C Control Register. When this interrupt occurs,
2
C Controller. When the SDA and SCL pin
2
2
C Controller continues the transaction. All
C Status Register and can only be cleared
START
Z8 Encore! XP
or
STOP
Product Specification
bit is set. The Not
®
F0822 Series
I2C Controller
128