ST72F361J7T3 STMicroelectronics, ST72F361J7T3 Datasheet - Page 111
ST72F361J7T3
Manufacturer Part Number
ST72F361J7T3
Description
IC MCU 8BIT 48K FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F361K6T6.pdf
(225 pages)
Specifications of ST72F361J7T3
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
LINSCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
34
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST72F36X-SK/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F361J7T3
Manufacturer:
STMicroelectronics
Quantity:
10 000
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SERIAL PERIPHERAL INTERFACE (cont’d)
10.6.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
Figure 72. Generic SS Timing Diagram
Figure 73. Hardware/Software Slave Select Management
– SS internal must be held high continuously
Figure
(if CPHA = 0)
(if CPHA = 1)
MOSI/MISO
Master SS
Slave SS
Slave SS
73).
SS external pin
SSI bit
Byte 1
SSM bit
1
0
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see
If CPHA = 1 (data latched on second clock edge):
If CPHA = 0 (data latched on first clock edge):
– SS internal must be held low during the entire
– SS internal must be held low during byte
Byte 2
SS internal
transmission. This implies that in single slave
applications the SS pin either can be tied to
V
ing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see
SS
, or made free for standard I/O by manag-
Byte 3
Section
Figure
10.6.5.3).
72):
ST72361
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