ST72F63BK6M1 STMicroelectronics, ST72F63BK6M1 Datasheet - Page 157
![MCU 8BIT LS USB 32KB FLSH 34SOIC](/photos/12/15/121510/497-34-soic_series_sml.jpg)
ST72F63BK6M1
Manufacturer Part Number
ST72F63BK6M1
Description
MCU 8BIT LS USB 32KB FLSH 34SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BK6M1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
34-SOIC (7.5mm Width)
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
19
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel / 8 bit, 12 Channel
For Use With
497-8428 - BOARD EVAL CHARGER ST7260/L6924D497-5521 - EVAL BOARD LOW SPEED USB497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5625-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
ST7263Bxx
EXTERNAL
Figure 73
resets:
●
●
●
When the LVD is enabled:
●
●
●
Figure 73. RESET pin protection when LVD is enabled
RESET
The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal
reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level
on the RESET pin can go below the V
Asynchronous RESET
Because the reset circuit is designed to allow the internal reset to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin is less than
the absolute maximum value specified for I
characteristics.
It is recommended not to connect a pull-up resistor or capacitor. A 10 nF pull-down
capacitor is required to filter noise on the reset line.
In case a capacitive power supply is used, it is recommended to connect a 1 MΩ pull-
down resistor to the RESET pin to discharge any residual voltage induced by the
capacitive effect of the power supply (this will add 5 µA to the power consumption of the
MCU).
Tips when using the LVD:
a)
b)
c)
Required
Check that all recommendations related to ICCCLK and reset circuit have been
applied (see notes above).
Check that the power supply is properly decoupled (100 nF + 10 µF close to the
MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to
put a 100 nF + 1 MΩ pull-down on the RESET pin.
The capacitors connected on the RESET pin and also the power supply are key to
avoid any start-up marginality. In most cases, steps a) and b) above are sufficient
for a robust solution. Otherwise: replace 10 nF pull-down on the RESET pin with a
5 µF to 20 µF capacitor.
and
0.01μF
Figure 74
1MΩ
Optional
show the reset circuit which protects the device against parasitic
pin. Otherwise the reset will not be taken into account internally.
Doc ID 7516 Rev 8
V
DD
R
ON
Filter
IL
max. level specified in
INJ(RESET)
GENERATOR
PULSE
in
Section Table 56.: Current
Electrical characteristics
Section Table 72.:
INTERNAL
RESET
WATCHDOG
LVD RESET
ST72XXX
157/186