Z8F4822AR020SG Zilog, Z8F4822AR020SG Datasheet - Page 64
Z8F4822AR020SG
Manufacturer Part Number
Z8F4822AR020SG
Description
IC ENCORE MCU FLASH 48K 64LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F4822AR020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-LQFP
Processor Series
Z8F482x
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4271
Z8F4822AR020SG
Z8F4822AR020SG
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Table 10. Stop Mode Recovery Sources and Resulting Action
PS019921-0308
Operating Mode
STOP mode
Stop Mode Recovery Using Watchdog Timer Time-Out
Stop Mode Recovery Using a GPIO Port Pin Transition HALT
Caution:
If the Watchdog Timer times out during STOP mode, the device undergoes a Stop Mode
Recovery sequence. In the Watchdog Timer Control register, the WDT and STOP bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
the Z8 Encore! XP F64XX Series devices are configured to respond to interrupts, the eZ8
CPU services the Watchdog Timer interrupt request following the normal Stop Mode
Recovery sequence.
Each of the GPIO Port pins may be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery. The GPIO Stop
Mode Recovery signals are filtered to reject pulses less than 10 ns (typical) in duration. In
the Watchdog Timer Control register, the STOP bit is set to 1.
Port Input Data registers record the Port transition only if the signal stays on
the Port pin through the end of the Stop Mode Recovery delay. Thus, short puls-
es on the Port pin can initiate Stop Mode Recovery without being written to the
Port Input Data register or without initiating an interrupt (if enabled for that
pin).
In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled. The
Stop Mode Recovery Source
Watchdog Timer time-out
when configured for Reset
Watchdog Timer time-out
when configured for interrupt
Data transition on any GPIO Port pin
enabled as a Stop Mode Recovery
source
Action
Stop Mode Recovery
Stop Mode Recovery followed by interrupt
(if interrupts are enabled)
Stop Mode Recovery
Z8 Encore! XP
Reset and Stop Mode Recovery
Product Specification
®
F64XX Series
50
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