Z8F4822AR020SG Zilog, Z8F4822AR020SG Datasheet - Page 187
Z8F4822AR020SG
Manufacturer Part Number
Z8F4822AR020SG
Description
IC ENCORE MCU FLASH 48K 64LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F4822AR020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-LQFP
Processor Series
Z8F482x
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4271
Z8F4822AR020SG
Z8F4822AR020SG
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PS019921-0308
Single-Shot Conversion
Continuous Conversion
Caution:
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. Follow the steps below for setting up the ADC and initiating a single-
shot conversion:
1. Enable the desired analog inputs by configuring the general-purpose I/O pins for
2. Write to the ADC Control register to configure the ADC and begin the conversion.
3. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
4. When the conversion is complete, the ADC control logic performs the following
5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
When configured for continuous conversion, the ADC continuously performs an analog-
to-digital conversion on the selected analog input. Each new data value over-writes the
previous value stored in the ADC Data registers. An interrupt is generated after each con-
version.
alternate function. This configuration disables the digital input and output drivers.
The bit fields in the ADC Control register can be written simultaneously:
–
–
–
–
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power-up
before beginning the 5129 cycle conversion.
operations:
–
–
–
powered-down.
the input signal bandwidth of the ADC and the latency of the ADC and its dig-
ital filter. Step changes at the input are not seen at the next output from the
ADC. The response of the ADC (in all modes) is limited by the input signal
bandwidth and the latency.
In CONTINUOUS mode, you must be aware that ADC updates are limited by
Write to the ANAIN[3:0] field to select one of the 12 analog input sources.
Clear CONT to 0 to select a single-shot conversion.
Write to the VREF bit to enable or disable the internal voltage reference generator.
Set CEN to 1 to start the conversion.
10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}.
CEN resets to 0 to indicate the conversion is complete.
An interrupt request is sent to the Interrupt Controller.
Z8 Encore! XP
Product Specification
Analog-to-Digital Converter
®
F64XX Series
173
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