EZ80F93AZ020SC00TR Zilog, EZ80F93AZ020SC00TR Datasheet - Page 123
![IC ACCLAIM MCU 64KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F93AZ020SC00TR
Manufacturer Part Number
EZ80F93AZ020SC00TR
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020SC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F93AZ020SC00T
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PS015313-0508
UART Line Control Register
This register is used to control the communication control parameters.
See
Table 60. UART Line Control Registers(UART0_LCTL = 00C3h, UART1_LCTL =
00D3h)
Bit
Position
1
CLRRXF
0
FIFOEN
Note: *Receive FIFO is not enabled during
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
DLAB
Note: *Receive Parity is set to SPACE in MULTIDROP mode.
Table 60
and
Value
0
1
0
1
Value
0
1
Table 61
Description
No effect.
Clear the receive FIFO, clear the receive error FIFO, and reset
the receive FIFO pointer. Valid only if the FIFO is enabled.
Transmit and receive FIFOs are disabled. Transmit and receive
buffers are only 1 byte deep.
Transmit and receive FIFOs are enabled*.
R/W
Description
Access to the UART registers at I/O addresses UARTx_RBR,
UARTx_THR, and UARTx_IER is enabled.
Access to the Baud Rate Generator registers at I/O addresses
UARTx_BRG_L and UARTx_BRG_H is enabled.
on page 118.
7
0
R/W
6
0
MULTIDROP
R/W
5
0
Universal Asynchronous Receiver/Transmitter
R/W
4
0
mode.
R/W
3
0
Product Specification
R/W
2
0
eZ80F92/eZ80F93
R/W
1
0
R/W
0
0
116
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