Z86E3116SSG Zilog, Z86E3116SSG Datasheet - Page 18

• Manufacturer Part Number: Z86E3116SSG
• Description: IC MICROCONTROLLER 2K 28-SOIC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E3116SSG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 16MHz
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: OTP
• Ram Size: 125 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: Z86E3xx
• Core: Z8
• Data Bus Width: 8 bit
• Data Ram Size: 125 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 3.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3968; Z86E3116SSG

DC ELECTRICAL CHARACTERISTICS (Continued)
Z86E30/E31/E40
Z8 4K OTP Microcontroller
Notes:
Standard Test Load
All timing references use 0.7 V
For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0.
18
1. When using extended memory timing, add 2 TpC.
2. Timing numbers given are for minimum TpC.
3. The V
No
10
11
12
13
14
15
16
17
18
20
1
2
3
4
5
6
7
8
9
the V
TdA(AS)
TwAS
TwDSW
TdDSR(DR)
ThDR(DS)
TdAS(A)
TdAS(DR)
TdAS(DS)
TwDSR
TdDS(A)
TdDS(AS)
TdR/W(AS)
TdDS(R/W)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)
TdDM(AS)
ThDS(AS)
CC
CC
voltage specification of 3.5V guarantees only 3.5V
Symbol
voltage specification of 5.5V guarantees 5.0V
Address Valid to AS Rise
Delay
AS Rise to Address Float
Delay
AS Rise to Read Data Req’d
Valid
AS Low Width
Address Float to DS Fall
DS (Read) Low Width
DS (Write) Low Width
DS Fall to Read Data Req’d
Valid
Read Data to DS Rise Hold
Time
DS Rise to Address Active
Delay
DS Rise to AS Fall Delay
R/W Valid to AS Rise Delay
DS Rise to R/W Not Valid
Write Data Valid to DS Fall
(Write) Delay
DS Rise to Write Data Not
Valid Delay
Address Valid to Read Data
Req’d Valid
AS Rise to DS Fall Delay
DM Valid to AS Fall Delay
DS Valid to Address Valid
Hold Time
CC
for a logic 1 and 0.2 V
Parameter
P R E L I M I N A R Y
CC
for a logic 0.
0.5V and
Note [3]
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
V
CC
T
Min
135
135
A
25
25
35
35
40
40
80
80
50
50
35
35
25
25
35
35
55
55
35
35
45
45
30
30
35
35
0
0
0
0
= 0 C to 70 C
16 MHz
Max
180
180
230
230
75
75
25
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS97Z8X0502
Notes
1,2
1,2
1,2
1,2
1,2
2
2
2
2
2
2
2
2
2
2
2
2
Zilog