Z8F2422VS020SG Zilog, Z8F2422VS020SG Datasheet - Page 63

• Manufacturer Part Number: Z8F2422VS020SG
• Description: IC ENCORE MCU FLASH 24K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2422VS020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z8F242x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F64200100KITG, ZENETSC0100ZACG, ZUSBSC00100ZACG, Z8F64210100ZDA, Z8F64210100ZDP, Z8F64210100ZDV, Z8F64220100ZDA, Z8F64220100ZDV, Z8F6422AR00ZEM, Z8F6422VS00ZEM, Z8F6421AN00ZEM
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4253; Z8F2422VS020SG

Stop Mode Recovery
PS019921-0308
External Pin Reset
On-Chip Debugger Initiated Reset
(unprogrammed) setting of the WDT_RES Option Bit. The
Control register is set to signify that the reset was initiated by the Watchdog Timer.
The RESET pin has a Schmitt-triggered input, an internal pull-up, an analog filter and a
digital filter to reject noise. Once the RESET pin is asserted for at least 4 system clock
cycles, the devices progress through the system reset sequence. While the RESET input
pin is asserted Low, the Z8 Encore! XP F64XX Series devices continue to be held in the
Reset state. If the RESET pin is held Low beyond the system reset time-out, the devices
exit the Reset state immediately following RESET pin deassertion. Following a system
reset initiated by the external RESET pin, the EXT status bit in the Watchdog Timer Con-
trol (WDTCTL) register is set to 1.
A Power-On Reset can be initiated using the On-Chip Debugger by setting the
the OCD Control register. The On-Chip Debugger block is not reset but the rest of the chip
goes through a normal system reset. The
reset. Following the system reset the
STOP mode is entered by the eZ8 executing a
information, see
are held in reset for 66 cycles of the Watchdog Timer oscillator followed by 16 cycles of
the system clock. Stop Mode Recovery only affects the contents of the Watchdog Timer
Control register. Stop Mode Recovery does not affect any other values in the Register File,
including the Stack Pointer, Register Pointer, Flags, peripheral control registers, and
general-purpose RAM.
The eZ8
and loads that value into the Program Counter. Program execution begins at the Reset
vector address. Following Stop Mode Recovery, the STOP bit in the Watchdog Timer
Control Register is set to 1.
actions.
™
CPU fetches the Reset vector at Program Memory addresses
Low-Power Modes
Table 10
on page 45. During Stop Mode Recovery, the devices
POR
lists the Stop Mode Recovery sources and resulting
RST
bit in the WDT Control register is set.
bit automatically clears during the system
STOP
instruction. For detailed STOP mode
Z8 Encore! XP
WDT
Reset and Stop Mode Recovery
status bit in the WDT
Product Specification
0002H
®
F64XX Series
and
RST
0003H
bit in
49