ST72F63BK2M1 STMicroelectronics, ST72F63BK2M1 Datasheet - Page 119
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ST72F63BK2M1
Manufacturer Part Number
ST72F63BK2M1
Description
IC MCU 8BIT 8K FLASH 34-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BK2M1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
34-SOIC (7.5mm Width)
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
27
Number Of Timers
2 x 16 bit
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit
For Use With
497-5521 - EVAL BOARD LOW SPEED USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72F63BK2M1
Manufacturer:
ST
Quantity:
20 000
ST7263Bxx
I²C Status register 1 (SR1)
Reset value: 0000 0000 (00h)
EVF
7
7 EVF Event flag
6 Reserved. Forced to 0 by hardware.
5 TRA Transmitter/Receiver.
4 BUSY Bus busy.
This bit is set by hardware as soon as an event occurs. It is cleared by software
reading SR2 register in case of error event or as described in
cleared by hardware when the interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
●
●
●
●
●
●
●
●
When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared
automatically when BTF is cleared. It is also cleared by hardware after detection of
Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface
is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
This bit is set by hardware on detection of a Start condition and cleared by
hardware on detection of a Stop condition. It indicates a communication in progress
on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
Note: The BUSY flag is NOT updated when the interface is disabled (PE=0). This
0
BTF=1 (Byte received or transmitted)
ADSL=1 (Address matched in Slave mode while ACK=1)
SB=1 (Start condition generated in Master mode)
AF=1 (No acknowledge received after byte transmission)
STOPF=1 (Stop condition detected in Slave mode)
ARLO=1 (Arbitration lost in Master mode)
BERR=1 (Bus error, misplaced Start or Stop condition detected)
Address byte successfully transmitted in Master mode.
can have consequences when operating in Multimaster mode; i.e. a second
active I
a conflict resulting in lost data. A software workaround consists of checking
that the I
TRA
2
C master commencing a transfer with an unset BUSY bit can cause
Doc ID 7516 Rev 8
2
C is not busy before enabling the I
BUSY
Read only
BTF
ADSL
2
C Multimaster cell.
On-chip peripherals
Figure
M/SL
48. It is also
119/186
SB
0